CDCVF2310PW .

The CDCVF2310PW is a high-performance low-skew Clock Buffer operates up to 200MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y(0:4) or 2Y(0:4) can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y(0:4) or 2Y(0:4) can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5 and 3.3V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.

• High-performance 1:10 clock driver
• Operates up to 200MHz at VDD 3.3V
• Output Enable Glitch Suppression
• Distributes one clock input to two banks of five outputs
• 25R On-chip series damping resistors
• <100ps at VDD 3.3V Pin-to-pin skew
• Green product and no Sb/Br

Applications

Horloge et synchronisation, Industrie

Avertissements

Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.